Job Summary
The Verification role will involve many aspects of functional verification using most effective methodologies in context of Subsystem/SoC/System Level. A strong ability to map requirements into a traceable verification plan is important. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation , debugging failures and creating simulation cases for various scenarios
Expectations include:
- Verification planning;
- Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs
- Development of direct and constrained-random stimulus
- Understands and analyzes RTL code, functional, assertion coverage results
- Understands and develops system Verilog assertions
- Strong skills in debug, failure re-creation and root cause analysis
- Applicant should have efficient debugging and logic skills
Job Qualifications
BTech/MTech with 5-10 years experience in SOC/Subsystem verification of complex multi-million gate designs with multiple clocks/power domains. Experience in below areas with strong hands on knowledge in below areas is needed
- C and UVM/SV based test environment,
- HDLs (Verilog/VHDL), simulators (Synopsys/Cadence/Mentor)
- Understanding of the design/architecture and ability to debug RTL/Gate netlist
- Coverage driven verification , regression management
- Microcontroller architecture, ARM Cores, Interconnect(NIC, FlexNoC), Cache Coherency
- Bus Protocols like AHB, AXI, ACE
- Following skills will have additional value:
- Memory controllers (Flash, SRAM,DDR3/4/LPDDR)
- Protocols like PCIe, MIPI, GPU (Graphics processing), VPU (Video Processing), Ethernet, USB, Image
- Formal verification methodologies and Apps, AVIP, PinMuxing Verification, Randomization
- Low Power intent verification using CPF, UPF
More information about NXP in India...
#LI-2734