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The Role and Impact:
As a Memory Electrical Validation Engineer, you will play a pivotal role in optimizing and validating electrical performance for memory IO interfaces. You'll focus on ensuring compliance with industry standards, analyzing margins for stable operation, debugging electrical issues, and driving system-level improvements. Your expertise will directly contribute to delivering high-quality, reliable products that meet production goals while advancing Intel's innovative memory solutions.
Business group
The Silicon and Platform Engineering (SPE) Group leads Intel's efforts in designing, developing, and validating advanced silicon and platform technologies. This team is committed to delivering cutting-edge solutions that drive Intel's leadership in the semiconductor industry. By joining SPE, you'll be part of a collaborative environment that tackles challenging problems and powers Intel's success in creating transformative technologies for the future.
Key Responsibilities
- Define electrical validation strategies for memory IO interfaces to ensure optimized electrical performance and alignment with production goals.
- Validate circuit analog performance, signal integrity compliance, and system-level margins against industry standards.
- Analyze, debug, and optimize Memory Reference Code (MRC) requirements to improve margins and overall product quality.
- Collaborate on multidisciplinary research for testing, validation, and optimization of memory IO and mixed-signal architectures.
- Develop procedures and designs for validation processes, systems margin evaluation, and test infrastructure.
- Debug functional and triage failures to identify root causes and resolve electrical issues.
- Test electrical interactions between design features using advanced validation infrastructure.
- Prepare validation specifications, evaluate intellectual property (IP), and generate detailed test reports.
- Partner with architecture, design, and presilicon verification teams to ensure effective Design for Testability (DFT) and Design for Manufacturability (DFM) capabilities for IO architectures.
Minimum Qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 3+ years of hands-on industry experience in electrical validation or debugging
- Proficiency in validating signal integrity and electrical performance of memory IO interfaces.
- Experience with debugging electrical and system-level issues.
- Demonstrated ability to analyze, design, and optimize validation procedures and test infrastructure.
- Familiarity with compliance testing against industry-standard specifications.
Preferred Qualifications:
- Familiarity with memory validation tools, techniques, and methodologies.
- Strong collaborative skills, particularly in multidisciplinary research and cross-functional teamwork.
- Proven ability to develop and refine validation strategies for complex architectures.
- Passion for delivering innovative solutions and driving continuous improvement.
We're looking for someone eager to make a meaningful impact while solving complex challenges in memory validation. If you're ready to join a team that values collaboration, innovation, and excellence, we encourage you to apply today.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.