Lead ASIC DFT Engineer at SAPSOL Technologies Inc. · Remote (United States)
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Strong hands-on experience in ASIC DFT with end-to-end ownership.
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Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
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Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
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Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
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Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
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Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
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Proven post-silicon debug and silicon bring-up experience.
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Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
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Why they ask: Opener to see how you frame your story.
How to answer: Two minutes: current role, one achievement that matches this job, why this company now.
Why they ask: Checks ownership and depth.
How to answer: Use situation, action, result. Quantify the result.
Why they ask: Tests accountability and learning.
How to answer: Pick a real failure, own your part, show the fix and what changed afterwards.
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Why they ask: Checks judgement under pressure.
How to answer: Describe a concrete framework and one example of a trade-off you made.
Why they ask: Looks for red flags and motivation.
How to answer: Stay positive: what you want next, not what you dislike.
Why they ask: Fit and ambition check.
How to answer: Tie your growth to the problems this team is solving.
Questions to ask them